1. Field of the Invention
The present invention relates to a circuit for converting line data to block data and a circuit for converting block data to line data in an image compressing system utilizing a discrete cosine transformation (DCT). In the following description, these converting circuits are called a line data-block converting circuit as a unified converting circuit.
2. Description of the Related Art
When an image is generally compressed by utilizing a discrete cosine transformation (DCT), no DCT processing can be performed with respect to a brightness signal and a color difference dot sequential signal as they are before balance modulation of these signals is performed by a subcarrier, especially, in a standard television system, concretely, in a National Television System Committee (NTSC) system and a Phase Alternation by Line (PAL) system. Namely, it is necessary to convert each of these signals to a block signal of longitudinal number n.times.transversal number n. In general, image data are received in the shape of line data so that it is necessary to convert data once blocked to line data. In this case, it is desirable to use a line data-block data converting circuit which all of plural operating modes of system clock frequencies different from each other can be set in both the NTSC and PAL system.
As shown in the following Table 1, there are four kinds of modes of the different system clock frequencies in the NTSC and PAL systems.
TABLE 1 ______________________________________ clock systems frequencies NTSC PAL ______________________________________ 13.5 MHz 720 720 858 864 14.3 MHz 768 910 14.1875 MHz 752 908 ______________________________________
For example, when a system clock frequency is set to 4.times.f.sub.SC =14.3 MHz (in this case, a frequency f.sub.SC of the subcarrier is equal to 3.58 MHz) in the NTSC system, the number of horizontal valid pixels on the screen is shown by an upper number in a corresponding column in Table 1 and is equal to 768. The total number of horizontal sampling pixels including a blanking area is shown by a lower number in the corresponding column in Table 1 and is equal to 910. Similarly, in a frequency mode of 13.5 MHz in the NTSC system, the number of horizontal valid pixels is equal to 720 and the total number of horizontal sampling pixels is equal to 858. In a frequency mode of 14.1875 MHz in the PAL system, the number of horizontal valid pixels is equal to 752 and the total number of horizontal sampling pixels is equal to 908. In a frequency mode of 13.5 MHz in the PAL system, the number of horizontal valid pixels is equal to 720 and the total number of horizontal sampling pixels is equal to 864.
In each of these various kinds of frequency modes, line data sequentially transmitted in rear time are converted to a block signal of longitudinal number n.times.transversal number n and are transmitted to a DCT section at the next stage in real time. To perform these converting and transmitting operations, the line data-block data converting circuit has a high speed static RAM (SRAM) and a memory controller for performing a writing operation of data while a reading operation of the data is performed. When the number of horizontal valid pixels on the screen in each of the frequency modes is set to b, the number of pixel blocks transmitted as a block of longitudinal number n.times.transversal number n for one horizontal period (H) is equal to b/(n.times.n). In this case, the memory controller transmits an initial address value represented by the following first general formula to the SRAM as address information every n horizontal periods (which are shown by nH in the following description). ##EQU1##
The memory controller accumulatively adds the initial address value every n pixels. When this added value is equal to or greater than the number b, it is necessary to subtract the number b from this added value and add one to this subtracted value. It is necessary to transmit this final added value as address information. In contrast to this, when the above accumulatively added value is smaller than the number b, it is necessary to transmit this accumulatively added value to the SRAM as address information as it is.
When block data are converted to line data, operations reverse to the above operations are performed. At this time, an initial address value every n horizontal periods (nH) is represented by the following second general formula. ##EQU2##
In this second general formula, BA.sub.(o) designates the number of valid pixels for one horizontal period and P designates BA.sub.(o) /n.
However, to realize a converting circuit represented by the above first and second formulas, it is necessary to dispose a divisional circuit and a modulo arithmetic (remaining) circuit so that the converting circuit is complicated. A method for storing calculated results in advance to a ROM table disposed in the memory controller has been considered to realize the converting circuit by a simplified circuit structure. However, in this method, it is necessary to dispose three ROM tables since the respective frequency modes are set by using the ROM tables. Therefore, the converting circuit is large-sized.